1. Field of the Invention
The present invention relates to a display device, and more particularly, to a driving circuit of a liquid crystal display (LCD) device and a method for driving the same, in which the number of data transmission lines and size of frequency are optimized.
2. Discussion of the Related Art
Recently, various flat panel displays having lighter weight and smaller volume than a cathode ray tube have been developed. Examples of the flat panel displays include a liquid crystal display (LCD) device, a field emission display (FED) device, a plasma display panel (PDP) device, and a light emitting display (LED) device.
In general, an LCD device includes a thin film transistor substrate, a color filter substrate, and a liquid crystal layer therebetween. The thin film transistor substrate includes a plurality of liquid crystal cells arranged in respective regions defined by a plurality of data lines and a plurality of gate lines, and a plurality of thin film transistors serving as switching elements formed in the respective liquid crystal cells. The color filter substrate includes a color filter layer. In particular, an LCD device displays desired images by generating an electric field across the liquid crystal layer in accordance with data signals supplied from the data lines, to thereby control light transmittance of liquid crystal molecules in the liquid crystal layer within the respective liquid crystal cells.
FIG. 1 illustrates an LCD device according to the related art. In FIG. 1, an LCD device includes an LCD panel 110, a timing controller 130, a data driver 140, and a gate driver 150. The LCD panel 110 includes liquid crystal cells defined by n gate lines GL1 . . . GLn and m data lines DL1 . . . DLm. The data driver 140 supplies analog data signals to the data lines DL1 . . . DLm, and the gate driver 150 supplies scan pulses to the gate lines GL1 . . . GLn. The timing controller 130 aligns externally inputted digital data signals RGB to be suitable for driving of the LCD panel 110, supplies the aligned digital data signals Data to the data driver 140, and controls the data driver 140 and the gate driver 150.
In the LCD panel 110, each of the liquid crystal cells includes a thin film transistor TFT serving as a switching element. The thin film transistor supplies data signals from the data lines DL1 . . . DLm to the liquid crystal cells in response to the scan pulses from the gate lines GL1 . . . GLn. The liquid crystal cell includes a common electrodes facing a pixel electrode with a liquid crystal material therebetween. The pixel electrode is connected to the thin film transistor TFT. Therefore, the liquid crystal cell is equivalent to a liquid crystal capacitor Clc. The liquid crystal cell also includes a storage capacitor Cst connected to a previous gate line to maintain the data signals in the liquid crystal capacitor Clc until the next data signals are applied thereto.
The timing controller 130 aligns the externally inputted digital data signals RGB to be suitable for driving of the LCD panel 110 and supplies the aligned digital data signals to the data driver 140. Also, the timing controller 130 generates data control signals DCS and gate control signals GCS using a main clock DCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync, which are externally inputted, to control driving of the data driver 140 and the gate driver 150.
Although not shown, the gate driver 150 includes a shift register that sequentially generates scan pulses, i.e., gate high pulses in response to the gate control signals GCS from the timing controller 130. In addition, the gate driver 150 includes a plurality of gate driver integrated circuits having the shift register.
FIG. 2 illustrates a connection structure between the timing controller and the data driver shown in FIG. 1. As shown in FIG. 2, the data driver 140 includes a plurality of data driver integrated circuits 242. Each of the data driver integrated circuits 242 receives the digital data signals Data supplied from the data transmission lines 222 and the data control signals DCS supplied from the control signal transmission lines 224. Each of the data driver integrated circuits 242 converts the digital data signals Data aligned from the timing controller 130 into the analog data signals in accordance with the data control signals DCS. Subsequently, the data driver integrated circuits 242 supply the analog data signals to the respective data lines DL1 . . . DLm of the LCD panel 110 (shown in FIG. 1) corresponding to one horizontal line per one horizontal period in which the scan pulses are supplied into the gate lines GL1 . . . GLn. In particular, each of the data driver integrated circuits 242 generates a plurality of gamma voltages having different voltage values corresponding to the number of gray levels of the data signals and selects one gamma voltage as the analog data signal depending on the gray level values of the digital data signals to supply the selected signal to the data lines DL1 . . . DLm.
In addition, the timing controller 130 converts the external digital source data RGB into transistor-transistor logic/complementary metal oxide semiconductor (TTL/CMOS) level depending on a CMOS interface mode and transmits the converted data signals Data to the data driver 140 in one port-to-one port mode or one port-to-two port mode. The timing controller 130 supplies the data signals Data of the TTL/CMOS level to the data transmission lines 222 and at the same time supplies the data control signals DCS to the control signal transmission lines 224.
Each of the data driver integrated circuits 242 is connected to the data transmission lines 222 and the control signal transmission lines 224 in common. Thus, the respective data driver integrated circuits 242 are sequentially driven depending on the data control signals DCS supplied from the control signal transmission lines 224 to receive the data signals from the data transmission lines 222 and convert the received data signals into the analog data signals to supply the converted signals to the respective data lines DL1 to DLm.
However, the aforementioned LCD device according to the related art has several problems. For example, the number of the data transmission lines between the timing controller and the data driver is not optimized, which causes the frequency or the size of the LCD increases greatly. In particular, as the size of the LCD device decreases, the number of the data transmission lines decreases but the frequency of the digital data signals supplied along the data transmission lines increases. On the other hand, as the size of the LCD increases, the number of the data transmission lines increases but the frequency of the digital data signals supplied along the data transmission lines decreases. Therefore, in the LCD device according to the related art, the number of the data transmission lines is not optimized, and its LCD size and the frequency are not balanced.